The design of complex integrated circuits (ICs), such as Central Processor Unit (CPU) chips, normally goes through several revisions, or turns, in silicon before the final production version is ready. These revisions could be a full turn, which includes metals and FET's, or a metal only turn in which only metal layers of the chip are changed. Fabrication of these turns is costly. As an example, for a current CPU, a full turn may cost on the order of one million dollars while a metal only turn may cost on the order of half a million dollars. A turn with a smaller number of metal layers changed (a partial metal turn) costs less. The cost is roughly proportional to the number of metal layers with its associated contacts, with lower level metal costing more. Reducing the number of metal layers that need to be changed helps to reduce the cost of fabrication. As an example, a design chip's first turn may only change one metal layer with the metal layer's associated contact.
The front side bus is the portion of an integrated circuit (IC) that is responsible for transporting data among the various subsystems and devices that make up the IC. In many integrated circuit applications, the performance of the front side bus of the integrated circuit is controlled by a collection of registers. As bus speed increases and the number of chips on the bus increase, the signal integrity of bus signals becomes more important. That is why many registers may be added to the CPU to change the associated bus parameters, such as driver termination, driver slew rate, receiver trip point, receiving deglitch delay, etc.
When the IC is in the design stages, it may undergo iterations of changes to the register values, where each iteration can require the fabrication of a new prototype IC. For each revision of the IC, the input/output performance of the front side bus of the IC is tested. If the bus performance does not meet design guidelines, then the IC layout is altered and a new IC revision fabricated. Clearly, the turnaround time of this process can be lengthy and affect the overall design time of the IC. Conversely, it can be seen that for an IC already in a production environment, having registers set to incorrect values can be catastrophic to the IC operation. This situation may occur if the design and prototyping was not done properly or it may be due to unforeseen system level impacts.
Referring now to FIG. 1, a block diagram of a fabrication process 100 for a circuit containing one or more registers is shown. After an IC containing one or more registers is designed (block 110), the IC is fabricated for testing (block 120). The IC is then tested for layout errors (block 130). If the IC test fails (block 140), then the register values must be changed during IC layout and the IC fabricated and tested again (blocks 120 and 130). The number of times the registers are changed, the layout changed and the IC fabricated and re-tested has a large impact on the overall cost and time-to-market of the IC. A second concern can occur if the IC passes the pre-production test and enters the production process (block 150). If an error is detected after the IC is in production (block 155), either due to a design flaw or an error in the previous test process of block 130, then the IC's that have been produced may not be usable, the IC layout will need to be modified (block 145) and the IC fabricated and tested again (blocks 120 and 130). Clearly detection of an error after production has started is undesirable, since many IC's may be wasted.